1. Field of the Invention
The invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure having a circuit structure and a fabrication method thereof.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and corresponding contacts of the packaging substrate, thus easily resulting in delamination of the conductive bumps from the packaging substrate. On the other hand, along with increased integration of integrated circuits, the CTE mismatch between the chip and the packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
Accordingly, the process having an interposer structure composed of semiconductor material is provided. A silicon interposer is disposed between the packaging substrate and the semiconductor chip. Since the silicon interposer is close in material to the semiconductor chip, the above-described drawbacks caused by a CTE mismatch can be effectively overcome.
Referring to FIG. 1 illustrates a schematic cross-sectional view of a conventional package structure having a silicon interposer. Such a conventional package structure overcomes the above-described drawbacks. In addition, compared with a package structure having a semiconductor chip directly disposed on a packaging substrate, the conventional package structure of FIG. 1 has a reduced layout area.
For example, a packaging substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the packaging substrate cannot be reduced, the area of the packaging substrate must be increased such that more circuits can be formed on the packaging substrate and electrically connected to the semiconductor chip having high I/O count. On the other hand, referring to FIG. 1, a plurality of semiconductor chips 11 are disposed on a silicon interposer 12 having through silicon vias (TSVs) 121 and the silicon interposer 12 is further disposed on a packaging substrate 13. As such, the semiconductor chips 11 are electrically connected to the packaging substrate 13 through the silicon interposer 12. Through a semiconductor process, the silicon interposer 12 can have a line width/pitch of 3/3 um or less. Therefore, the area of the silicon interposer 12 is sufficient for electrical connection with the semiconductor chips 11 having high I/O counts and hence the area of the packaging substrate 13 does not need to be increased. Further, the fine line width/pitch of the silicon interposer 12 facilitates to shorten the electrical transmission path. Therefore, compared with semiconductor chips directly disposed on a packaging substrate, the semiconductor chips 11 disposed on the silicon interposer 12 can achieve a higher electrical transmission speed (efficiency).
However, the TSVs 121 of the silicon interposer 12 used for electrically connecting the semiconductor chip 11 and the packaging substrate 13 incur a high fabrication cost. In addition, the silicon interposer 12 leads to an increase of the thickness of the final package structure.
Therefore, how to overcome the above-described drawbacks has become critical.